1. Field of the Invention
Generally, the present disclosure relates to the manufacture of sophisticated semiconductor devices, and, more specifically, to various methods of forming fins for a FinFET device wherein the fins have a high germanium content.
2. Description of the Related Art
The fabrication of advanced integrated circuits, such as CPU's, storage devices, ASIC's (application specific integrated circuits) and the like, requires the formation of a large number of circuit elements in a given chip area according to a specified circuit layout, wherein so-called metal oxide field effect transistors (MOSFETs or FETs) represent one important type of circuit element that substantially determines performance of the integrated circuits. A FET is a device that typically includes a source region, a drain region, a channel region that is positioned between the source region and the drain region, and a gate electrode positioned above the channel region. Current flow through the FET is controlled by controlling the voltage applied to the gate electrode. If a voltage that is less than the threshold voltage of the device is applied to the gate electrode, then there is no current flow through the device (ignoring undesirable leakage currents, which are relatively small). However, when a voltage that is equal to or greater than the threshold voltage of the device is applied to the gate electrode, the channel region becomes conductive and electrical current is permitted to flow between the source region and the drain region through the conductive channel region. The above description is applicable for both the N-type FET as well as the P-type FET, except that the polarity of voltage in operation and the doping type of the source, the channel and the drain regions are correspondingly reversed. In so-called CMOS (Complementary Metal Oxide Semiconductor) technology, both N-type and P-type MOSFETs (which are referred to as being “complementary” to each other) are used in integrated circuit products. CMOS technology is the dominant technology as it relates to the manufacture of almost all current-day large scale logic and memory circuits.
To improve the operating speed of FETs, and to increase the density of FETs on an integrated circuit device, device designers have greatly reduced the physical size of FETs over the years. More specifically, the channel length of FETs has been significantly decreased, which has resulted in improving the switching speed of FETs. However, decreasing the channel length of a FET also decreases the distance between the source region and the drain region. In some cases, this decrease in the separation between the source and the drain makes it difficult to efficiently inhibit the electrical potential of the channel from being adversely affected by the electrical potential of the drain, which is commonly referred to as a “punch-through” of the electrical potential from the drain to the source and leads to larger leakage currents. This is sometimes referred to as a so-called short channel effect, wherein the characteristic of the FET as an active switch is degraded.
In contrast to a planar FET, which has a planar structure, there are so-called three-dimensional (3D) devices, such as an illustrative FinFET device, which is a three-dimensional structure. More specifically, in a FinFET, a generally vertically positioned, fin-shaped active area is formed and a gate electrode encloses both of the sides and the upper surface of the fin-shaped active area to form a “tri-gate” structure so as to use a channel having a 3D “fin” structure instead of a planar structure. In some cases, an insulating cap layer, e.g., silicon nitride, is positioned at the top of the fin and the FinFET device only has a dual-gate structure. Unlike a planar FET, in a FinFET device, a channel is formed perpendicular to a surface of the semiconducting substrate so as to reduce the depletion width in the “fin” channel (as a result of the better electrostatic characteristics of the tri-gate or dual-gate structure around the fin channel) and thereby reduce so-called short channel effects. Also, in a FinFET, the junction capacitance at the drain region of the device is greatly reduced, which tends to reduce at least some short channel effects.
When an appropriate voltage is applied to the gate electrode of a FinFET device, the surfaces (and the inner portion near the surface) of the fins, i.e., the substantially vertically oriented sidewalls and the top upper surface of the fin with inversion carriers, contributes to current conduction. In a FinFET device, the channel width is approximately two times (2×) the vertical fin height plus the width of the top surface of the fin, i.e., the fin width. Multiple fins can be formed in the same footprint as that of a planar transistor device. Accordingly, for a given plot space (or footprint), FinFETs tend to be able to generate significantly stronger drive current than planar transistor devices. Additionally, the leakage current of FinFET devices after the device is turned “OFF” is significantly reduced as compared to the leakage current of planar transistor devices due to the superior gate electrostatic control of the “fin” channel on FinFET devices. In short, the 3D structure of a FinFET device is a superior MOSFET structure as compared to that of a planar transistor, especially in the 20 nm CMOS technology node and beyond. FinFETs have been demonstrated on both standard silicon substrates (bulk FinFETs) and on silicon-on-insulator (SOI) substrates.
The drive current capability of an N-type transistor device is determined based upon the mobility of electrons in the semiconducting substrate. Conversely, for a P-type transistor device, the drive current capability of the device depends upon the mobility of holes in the semiconducting substrate. Historically, both N-type devices and P-type devices were formed in a substrate comprised of silicon.
FIGS. 1A-1F depict one illustrative prior art technique for forming silicon/germanium fins for a FinFET device 10. FIG. 1A depicts the device 10 after several process operations have been performed. Initially, a plurality of trenches 14 were etched into a silicon substrate 12 using known masking and etching processes and the trenches 14 were overfilled with a layer of insulating material 18, such as silicon dioxide. Thereafter, a chemical mechanical polishing (CMP) process was performed to planarize the upper surface of the insulating material 18 with the top of the fins 16 (or the top of a patterned hard mask (not shown)). Next, as shown in FIG. 1B, an etching process was performed to remove the silicon fins 16 and thereby define a plurality of cavities 20 in the layer of insulating material 18. FIG. 1C depicts the device 10 after an epitaxial deposition process was performed to form silicon/germanium fins 22 and after an optional CMP process was performed to planarize the upper surface of the silicon/germanium fins 22 with the upper surface of the layer of insulating material 18. The silicon/germanium fins 22 were typically formed so as to have a germanium concentration that fell within the range of about 20-80%. Next, as shown in FIG. 1D, a timed etching process was performed to remove portions of the exposed silicon/germanium fins 22 which resulted in the formation of the depicted cavities 24. FIG. 1E depicts the device 10 after another epitaxial deposition process was performed to form germanium-rich silicon/germanium material 26 in the cavities 24 and an optional CMP process was performed to planarize the upper surface of the germanium-rich silicon/germanium material 26 with the upper surface of the layer of insulating material 18. The germanium concentration of the germanium-rich silicon/germanium material 26 was typically greater than the germanium concentration of the silicon/germanium fins 22. In one example, the germanium concentration of the germanium-rich silicon/germanium material 26 was typically about 40-100%. FIG. 1F depicts the device 10 after an etching process was performed to recess the layer of insulating material 18 between the fins and thereby expose the upper portions of the fins, which corresponds to the final fin height of the fins. At the point of fabrication depicted in FIG. 1F, traditional manufacturing operations would then be performed to complete the fabrication of the device 10, e.g., formation of a gate structure, formation of doped regions, etc. While the prior art process described above is known to those skilled in the art, the industry needs a new and novel method of forming silicon/germanium fins on FinFET devices.
The present disclosure is directed to various methods of forming fins for a FinFET device, wherein the fins have a high germanium content, that may solve or reduce one or more of the problems identified above.